Question

Please explain the principle of operartion of NMOS and PMOS and how this relates to all the operations of NMOS and PMOS (triode, cutoff, saturation) with respect to the gate, drain, collector)

Answer 1

NMOS:

NMOS is built with n-type source and drain and a p-type substrate,

In a NMOS, carriers are electrons

When a high voltage is applied to the gate, NMOS will conduct

When a low voltage is applied in the gate, NMOS will not conduct

NMOS are considered to be faster than PMOS, since the carriers in NMOS, which are electrons, travel twice as fast as holes.

NMOS ICs would be smaller than PMOS ICs

NMOS can provide one-half of the impedance provided by a PMOS

NMOS represents N type MOS transistor.

PMOS:

PMOS is built with p-type source and drain and a n-type substrate.

PMOS, carriers are holes.

When a high voltage is applied to the gate, PMOS will not conduct

When a low voltage is applied in the gate, PMOS will conduct

Which are the carriers in PMOS.

PMOS devices are more immune to noise than NMOS devices.

PMOS represents P type MOS transistor.

Operation:

Pmos passes good “1”-Vdd

Nmos Passes good “0”-gnd

Let me explain

nMOS - works when input to gate is high-eq1
pMOS - works when input to gate is low. -eq2

The threshold is +ve for nMOS and -ve for pMOS.
The source of pMOS is connected to VDD and nMOS to VSS.:In the figure given below

We know current will always conduct when there will be a channel i.e Vgs>Vt(threshold voltage) Suppose Vt=1volt

For Pmos:(Vt=-1 volt for Pmos vt is negetive)

When Vs is connected to Vdd :

Vg=0

Vs=5

Vgs=vg-vs=-5 volt

since |vgs|> |vt| ,it conducts normally

i.e Vout=Vdd (5volt)-no drop ,full efficiency

Whne Pmos connections are interchanged:

Vs=gnd =0

Vg=o (eq2) vgs=ovolt

|vgs|<|Vt|

No conduction it cannot 0 volt

Thats why P,os is called good 1(vdd connected to vs)

2. For Nmos:(Vt=1 volt ,for nmos vt is positive)

When In normal operation suppose

Vg = 5v and

Vs = 0v and
Fot the above mentioned case Vgs=Vg-Vs
=5v

which is
grater than threshold voltage and logic 0 will easily pass.
Now if we want to pass logic 1, we have to make Vs=Vdd
(Suppose 5v). In this case Vgs=0v which is less than
threshold voltage, thus channel is not formed. And a bad
logic 1 is passed. rather than

vout=Vdd, there will be a loss equivalent to vt

Vout=Vdd-Vt ( full efficieny is not achieved)

So Nmos is a good 0″(gnd) and bad 1(vdd)

PS: bad because see we are not getting output as Vdd , we are getting( Vdd- Vt)

a loss of efficieny