Question

1. What is the purpose of the XDC file?

1. Simulate the behavioral code
2. Map the I/O from VHDL to Basys3 Board
3. Edit the Basys3 Board device type
4. Run the synthesis

2. What is the purpose of declaring a “signal”?

3. Which file contains the list of input combinations used to simulate a circuit in Xilinx Vivado?  

1. XDC
2. Design
3. Testbench

4. What is the purpose of using ieee.std_logic_unsigned.alL or ieee.std_logic_signed.all in lab4 and lab6 testbench2?

Answer 1

The XDC file is the printer description in XML format, which the Adobe Document Services require to create your print files. PDF documents can only be printed on printers of SAP device types for which there is an XDC file on the Adobe Document Server.

a. To Perform Behavioral Simulation

1. Compile the HDL simulation libraries (VHDL/Verilog UNISIM, SIMPRIM, XilinxCoreLib, SmartModels).

• In the Design panel, select Behavioral Simulation from the Design View drop-down list.
• In the Hierarchy pane, select a test bench file or an HDL source file to simulate.
• In the Processes pane, expand ISim Simulator or ModelSim Simulator.
• Right-click Simulate Behavioral Model, and select Process Properties.
• In the Process Properties dialog box, set the following properties:
  • For ISim, set the ISim Properties.
  • For the ModelSim simulator, set the Simulation Properties and Display Properties.
• Double-click Simulate Behavioral Model.

A simulation execution script is created and invoked by the simulator. The files that are passed to the simulation include the following:

• Test bench file.
• Design VHDL or Verilog file or any associated core files for simulation.

Part C:-

The Basys 3 board includes sixteen slide switches, five push buttons, sixteen individual LEDs, and a four-digit sevensegment display.The pushbuttons and slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). The five pushbuttons, arranged in a plus-sign configuration, are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. Slide switches generate constant high or low inputs depending on their position.

The sixteen individual high-efficiency LEDs are anode-connected to the FPGA via 330 ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs, which are not useraccessible, indicate power-on, FPGA programming status, and USB port status.

A signal declaration contains one or more identifiers (i.e. more than one signal can be declared in one statement) and a subtype indicator. Each signal name is an identifier and creates one separate signal. The (sub)type in the signal declaration can be of any scalar or composite type. Optionally, it may have some constraints. File and access types are not allowed for signals.

A signal can be assigned an initial value in its declaration. It the value is produced by an expression, it must be of the same type as the signal itself. If there is no expression given in the signal declaration, then the default value of the signal is the left bound of the specified type

A signal may be declared with a signal_kind statement, which can be either a register or bus. Such signal must be of a resolved type. A register type signal retains its current value even when all its drivers are turned off. However, the signal_kind bus relies on the resolution function to supply a "no-drive" value.

The file which contains the list of input combinations used to simulate a circuit in Xilinx Vivado is Verlilog Template (VEO) files that contain code that can be used as a model for instantiation and simulating a circuit in Xilinx Vivado.

The Std_logic_1164 package is the IEEE standard for describing digital logic values in VHDL (IEEE STD 1164). ... It also contains VHDL functions for these types to resolve tri-state conflics, functions to define logical operators and conversion functions to and from other standard type.

The IEEE created the IEEE VHDL library and std_logic type in standard 1164. This was extended by Synopsys; their extensions are freely redistributable. Parts of the IEEE library can be included in an entity by inserting lines like these before your entity declaration: library ieee; use ieee. std_logic_1164.