Question

In: Electrical Engineering

Consider two different implementations of the same instruction set architecture. The instructions can be divided into...

Consider two different implementations of the same instruction set architecture.

The instructions can be divided into four classes according to their CPI (classes A, B, C, and D).

P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2, and 2.

Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows:

10% class A, 20% class B, 50% class C, and 20% class D,

which is faster: P1 or P2?

a. What is the global CPI for each implementation?

b. Find the clock cycles required in both cases.

Solutions

Expert Solution

Total instructions - 106

No. of class A instructions = 10/100* 106 = 105

No. of class B instructions = 20/100* 106 = 2*105

No. of class C instructions = 50/100* 106 = 5*105

No. of class D instructions = 20/100* 106 = 2* 105

For P1:

CPIs are: 1, 2, 3, 3

Thus total CPIs = 1* 105 + 2* 2 *105 + 3* 5 *105 + 3* 2*105 ( sum of CPI of that class * no. of instructions of a particular class ) = 26 * 105

THus CPU time = 26 * 105/ clock rate = 26 * 105 / 2.5 * 109 = 10.4*10-4 sec

For P2:

CPIs are: 2, 2, 2, 2

Total CPIs = 2 * 105 + 2* 2 *105 + 2* 5 *105 + 2* 2*105 ( sum of CPI of that class * no. of instructions of a particular class ) = 20 * 105

THus CPU time = 20 * 105/ clock rate = 20 * 105 / 3 * 109 = 6.67*10-4 sec

Thus P2 is faster.

a. Global CPI = (CPU-Time x Clock Rate)/ total instructions

CPI (P1) = 10.4 × 10−4 × 2.5 × 109/106 = 2.6

CPI (P2) = 6.66 × 10−4 × 3 × 109/106 = 2.0

b. CLock cycles required in P1= 1* 105 + 2* 2 *105 + 3* 5 *105 + 3* 2*105 ( sum of CPI of that class * no. of instructions of a particular class ) = 26 * 105

CLock cycles required in P2= 2 * 105 + 2* 2 *105 + 2* 5 *105 + 2* 2*105 ( sum of CPI of that class * no. of instructions of a particular class ) = 20 * 105


Related Solutions

Consider two different implementations of the same ISA. There are four classes of instructions, Arithmetic, Store,...
Consider two different implementations of the same ISA. There are four classes of instructions, Arithmetic, Store, Load, and Branch. The clock rate and CPI of each implementation are given in the following table.              Clock Rate                  CPI-Arithmetic CPI-Store             CPI-Load    CPI-Branch P1           2.0 GHz                        1                                     2 3                                4 P2           2.5 GHz                        2    2 2                             2 Given a program with 10^6 instructions divided into classes as follows: 10% Arithmetic, 20% Store, 50% Load, and 20% Branch, which implementation is faster?
Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a...
Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. a. Find execution time for each processor for a program with 2 x 10 9 instructions. Which one is the fastest? b. If the processors each execute a program in...
Consider three different processors P1, P2, and P3, executing the same instruction set. P1 has a...
Consider three different processors P1, P2, and P3, executing the same instruction set. P1 has a clock cycle time of 300 picosecond and a CPI (clock cycles per instruction) of 1.5. P2 has a clock cycle time of 400 picosecond and a CPI of 1.0. P3 has a clock cycle time of 250 picosecond and a CPI of 2.0. P1 is running a program with 10 instructions. P2 is running a different program with 20 instructions. P3 is running a...
Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a...
Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. a. Which processor has the highest performance expressed in instructions per second? b. If the processors each execute a program in 10 seconds, find the number of cycles and the...
Consider three different processors P1, P2 and P3 executing the same instruction set with clock rates...
Consider three different processors P1, P2 and P3 executing the same instruction set with clock rates and CPI given in the following table: Processor Clock Rate CPI P1 2 GHz 1.5 P2 1.5 GHz 1.0 P3 3 GHz 2.5 c) We are trying to reduce the execution time by 30% but this leads an increase of 20% in the CPI. What clock rate should we have to get this time reduction? b) If the processors each execute a program in...
Write a possible assembly language instruction or set of instructions to accomplish the following: a) Compare...
Write a possible assembly language instruction or set of instructions to accomplish the following: a) Compare the byte stored at the memory location pointed to by register R4 to the upper (higher) byte stored in register R5 b) Branch to instruction at label ‘ZERO’ if the lower byte of register R6 is zero c) Jump to the instruction at label ‘EVEN’ if the value in register R7 is an even number
2 – The CPU design team is designing an instruction set with three classes of instructions....
2 – The CPU design team is designing an instruction set with three classes of instructions. Parameters are given in the following table. Consider a program with 65% ALU instructions, 20% memory access instructions, and 15% control instructions. What is the average CPI for this CPU? Clock Rate: 4GHz CPI for ALU Inst.: 4 CPI for Memory Inst.: 8 CPI for Control Inst.: 2
Assume a non-pipelined processor takes 100 ns to process an instruction. The same instruction can be...
Assume a non-pipelined processor takes 100 ns to process an instruction. The same instruction can be executed in a 5-stage pipelined processor, where each stage takes 20 ns. (i) What is the minimum number of instructions for which the speedup achieved by the pipelined processor compared to the non-pipelined processor is at least 4? (ii) The instruction takes the same time (100 ns) to execute whether on the pipelined processor or on the non-pipelined processor. So why do we say...
Topics 1. Introduction 2. MIPS instruction set architecture (ISA) Exercise 1 Answer the following questions. (a)...
Topics 1. Introduction 2. MIPS instruction set architecture (ISA) Exercise 1 Answer the following questions. (a) List the five classic components of a computer. (b) Describe the steps that transform a program written in a high-level language such as Java into a representation that is directly executed by a computer processor.
ASAP Plz help CSC 263 computer architecture and organization Describe 3 different types of Instructions of...
ASAP Plz help CSC 263 computer architecture and organization Describe 3 different types of Instructions of MIPS architecture: Description should include: - Instruction format - Field descriptions - Example instructions of each type
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT