Question

In Verilog, what are three ways of preventing latch inference in case statements?

Answer 1

1.Include all possible cases in the case statement.

always @ (SEL or DIN1 or DIN2)

begin

case (SEL)

2'b00 : DOUT <= DIN1 + DIN2;

2'b01 : DOUT <= DIN1 - DIN2;

2'b10 : DOUT <= DIN1;

endcase

end

This example will create latches because there is no provision for the case when SEL = "11". To eliminate the latches, add another entry to address this possibility.

2. 2'b11 : DOUT <= DIN2;

Using the DEFAULT clause (Verilog) will always work, but this may create extraneous logic. This always the safest methodology, but it may create a larger and slower design, as any unknown state will have logic to bring it to a known state.

3. always @ (SEL or DIN1 or DIN2)

begin

case (SEL)

2'b00 : DOUT <= DIN1 + DIN2;

2'b01 : DOUT <= DIN1 - DIN2;

2'b10 : DOUT <= DIN1;

2'b11 :

begin

DOUT <= DIN2;

TEMP <= DIN1;

end

endcase

end

This example will infer latches because the "11" case assigns two outputs, while the others only assign one. Looking at this case from TEMP's point of view, only one of four possible cases are specified, so it is incomplete.

Avoid this situation by assigning values to the exact same list of outputs for each case.