Question

We want to make a machine that detects an alternating pattern. It should indicate whether

three or more alternating bits have been observed on our serial input X. So, if X has 010 or

101, the output Z will be high, otherwise the output will be low. Assume that when the

machine starts up or is reset, is has not seen any bits of data to work with and the output

cannot go high until it sees the third bit of data.

Your task is to design two CONCEPTUALLY different synchronous state machines (Mealy

and Moore) in Logisim. You can use either J-K or D flip-flops.

Your Task:

Make the State Diagram

Make the State Assignments

Make the State Transition Table

Make the K-Maps

Derive the Equations

Implement in Logisim

Answer 1

Mealy FSM

There are 5 different states as shown in Mealy State diagram. We use binary state encoding.

S0 = 000,             S1 = 001,             S2 = 010,             S3 = 011,             S4 = 100

STATE	PRESENT STATE			INPUT	NEXT STATE			OUTPUT
	Q2	Q1	Q0	X	Q2+	Q1+	Q0+	Z
S0	0	0	0	0	0	0	1	0
	0	0	0	1	0	1	1	0
S1	0	0	1	0	0	0	1	0
	0	0	1	1	0	1	0	0
S2	0	1	0	0	0	0	1	1
	0	1	0	1	0	1	1	0
S3	0	1	1	0	1	0	0	0
	0	1	1	1	0	1	1	0
S4	1	0	0	0	0	0	1	0
	1	0	0	1	0	1	1	1
S5	1	0	1	0	X	X	X	X
	1	0	1	1	X	X	X	X
S6	1	1	0	0	X	X	X	X
	1	1	0	1	X	X	X	X
S7	1	1	1	0	X	X	X	X
	1	1	1	1	X	X	X	X

Moore FSM

There are 7 different states shown in Moore State diagram. We use binary state encoding.

S0 = 000,             S1 = 001,             S2 = 010,             S3 = 011,             S4 = 100,             S5 = 101,           S6 = 110

STATE	PRESENT STATE			INPUT	NEXT STATE			OUTPUT
	Q2	Q1	Q0	X	Q2+	Q1+	Q0+	Z
S0	0	0	0	0	0	0	1	0
	0	0	0	1	1	0	0	0
S1	0	0	1	0	0	0	1	0
	0	0	1	1	0	1	0	0
S2	0	1	0	0	0	1	1	0
	0	1	0	1	1	0	0	0
S3	0	1	1	0	0	0	1	1
	0	1	1	1	0	1	0	1
S4	1	0	0	0	1	0	1	0
	1	0	0	1	1	0	0	0
S5	1	0	1	0	0	0	1	0
	1	0	1	1	1	1	0	0
S6	1	1	0	0	1	0	1	1
	1	1	0	1	1	0	0	1
S7	1	1	1	0	X	X	X	X
	1	1	1	1	X	X	X	X

Moore Machine Circuit