Question

al to
zero at the same time.
3- To realize {Y-CD+AB-EG} the required number of two-input:
AND and OR gates are: 2, 3 respectively.
4- In Denorgan's theorem OR gate is a negativeNAND gate

Put T or F for the following statements and if any is (F) correct the
wrong part without changing the underline words.
1- The expression which is its output equal to X' is: X NOR 1.
2- In any asynchronous flip flop, the clock and clear must not equal to
zero at the same time.
3- To realize {Y=CD+AB+EG) the required number of two-input;
AND and OR gates are: 2, 3 respectively.
4- In Demorgan's theorem OR gate is a negative NAND gate.

Answer 1

Part 1 :The expression which is its output equal to X' is: X NOR 1.
It is False becuase X NOR 1 = (X OR 1)'
   = X' AND 0 [By Demorgan's Law ]
= 0 [ As X AND 0 =0 By Domination Law ]
As 0 is not equal to X' so answer is False.
We can correct it by having NAND instead of NOR. So, X NAND 1 = (X AND 1 )'
   = X' OR 0    [By Demorgan's Law ]
= 0 [ As X' OR 0 = X' By Identity Law ]

Therefore, Answer is false And we can correct it as : X NAND 1 [ As  X NAND 1 =X' ]

Part 2:  In any asynchronous flip flop, the clock and clear must not equal to zero at the same time.

Answer is false because Asynchronous inputs (preset and clear ) on a flip-flop have control over the outputs (Q and not-Q) regardless of clock input status.

As the clear input has control over the output of flip flop regardless of clock input status.
Therefore, clock and clear can be zero at the same time.

Therefore, Answer is False.

Part 3:  To realize {Y=CD+AB+EG) the required number of two-input; AND and OR gates are: 2, 3 respectively.
It is false because we required 3 AND gates and 2 OR gates.

• 1 AND gate to calculate CD.
• 1 AND gate to calculate AB.
• 1 AND gate to calculate EG.
• 1 OR gate to compute CD +AB
• 1 OR gate to compute ( CD + AB ) +EG

Therefore, Answer is False and we required 3 AND gates and 2 OR gates.

Part 4: In Demorgan's theorem OR gate is a negative NAND gate.

Answer is false if we will do negatiation of NAND gate : Negatiation of ( NAND) =(NAND) '
   =AND [By Demorgan's law]
So negative of NAND is AND .Therefore, Negative of OR gate is NOR gate.
Therefore, Answer is False as  Negative of OR gate is NOR gate so we required NOR gate instead of NAND.