Question

D-Latch is a simple clocked memory element in which the output is equal to the stored

state inside the element.

In D-Latch the state is changed whenever the appropriate inputs change and the clock is

asserted. A D-Latch has two inputs and two outputs.

The inputs are the data value to be stored and a clock signal that indicates when the latch should read the value on the data input and store it. The outputs are simply the value of the internal state and its complement.

When the clock input is asserted, the latch is said to be open, and the value of the output becomes the value of the data input. When the clock input is de-asserted, the latch is said to be closed, and the value of the output is whatever value was stored the last time the latch was open.

1. What is the difference between DFF and D-Latch?

2. Can one chip be used for constructing the other? Explain.

Answer 1

Solution)

1 In the configuration of enabling the latches are transparent in nature, the leches are enabling the output Q will be followed the D input for entire change of in D. The latch of D will using to capturing, or the "latch" It was the level of logic which will presenting on the line of data whenever the input of clock is heavy then the Q output will following the input D. When ever the iput of clock falling to 0 of logic the end stage of input D is trapping and helding in the latch. So aschynchronous of latch so that they are can't triggering.

The edge triggered of flip-flops the Q output will be only following the D edging of the clock so it's only depending on design of flip-flops if it raise or fall. The work of flip-flops D is same as latch of D excepting the D flip-flop output taking the input of D at the situation of positive edging at pin of the clock and delaying it by the clock cycle of one so this is the reason so it was generally called as delaying flip-flop. The flip-flop of D could be interrupting as the line of delaying line or oder of zero hold. The pros of flip-flop D is overing the type of D "latches of transparent" Is that the signaling on the input pin of D is capturing the flip-flop moments is clocking and the input D changes would be ignoring, till the event of next clock.

2 the latches could be builting the flip-flop and the could be builting from the gates and the flip-flop could be builting from the latch the asynchronous of latches so it means the changes of output is done very easy after the changes of the input, the many of the computer systems are in synchronized which could means that the sequence if the circuit of output is changing simultaneous way to the global clocking rhythm signals. So flip-flop is version of asynchronous of the latching so that the latches could be combining and making a flip-flop.

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