In: Physics
Question 1
Silicon dioxide was used as the standard interlayer dielectric (ILD) until the 0.13μm CMOS process was introduced, when it was replaced by low-k dielectrics which have lower dielectric constants to the reduce capacitance between wires.
Select one:
True
False
2.
Chemical vapor deposition (CVD) provides much better step coverage than sputtering, and so can be used to cover both vertical and horizontal surfaces with the same thickness.
Select one:
True
False
3.
The first step performed when fabricating a PN junction diode is to implant the N-type material into the P-type wafer.
Select one:
True
False
4.
Flip-chip packaging of chips :
Select one:
a. All of these
b. Makes electrical connections using bumps on the surface of the chip
c. Places the chip in the package upside down
d. Can be used at signal frequencies well above a few GHz
e. Uses metal bumps which can be placed anywhere on the surface of the chip
5.
Which of the following will decrease the thickness of a grown layer of silicon dioxide?
Select one:
a. Removing water vapor from the ambient gas in the furnace
b. All of these
c. Decreasing the furnace temperature
d. Decreasing the oxidation time in the furnace
e. None of these
1. True. silicon dioxide has been replaced by low k dielectric to reduce capacitance, enabling switching speed and lower heat dissipation.
2. False. sputtering takes place at higher pressure, due to which scattering of atoms is more, increasing step coverage.
3. False, in pn junction fabrication, a p type material is implanted upon a n type wafer.
4. all of the mentioned statements describe the properties of flip chip. option a is the answer.
5. presence of water vapour increases the thickness. so removing it will reduce the thickness.
high temperature results in high oxidation rate. hence reducing temperature will reduce the thickness.
high oxidation rate results in increased oxide layer thickness. hence lowering oxidation time will decrease the thickness. all of them are correct. option b is the answer.