Question

1)Regarding the UTB(ultra-thin-body) MOSFET, why do they use the raised source/drain technique ?

2)In the FinFET having the Fin height, H_fin, and Fin width, W_fin, , What is the channel width of MOSFET, W?

3)Compare the three FinFET structures; tall, short and nanowire FinFET

4)Explain how FinFET can have shorter L_g, lower I_off, and larger I_on than a single-gate MOSFET.

Answer 1

(3)

Nanowires and FinFETs are useful due to their proven robustness against Short-Channel Effects (SCE) and relatively simple fabrication. Silicon nanowire FinFET (SNWFT) is being considered as the candidate for CMOS scaling beyond the 32 nm node due to its high performance, excellent gate control and enhanced carrier transportation properties. Thin and multi-gate controlled body provide FinFETs a superior short-channel effect control, electrostatic shielding from the body bias, relaxing channel doping or pocket implants, commonly needed in planar technologies to avoid threshold voltage (VTH) roll-off. Adequate device VTH is now being achieved by using gate stack engineering. Metal-Gates with High-k (HKMG) dielectric stacks provide the desired VTH by work-function tuning as well as preserving low gate leakage. Various process options are being attempted to affect carrier transport in a different manner. The use of metal gates as replacement for Poly-Si stacks eliminates the Poly-depletion effect, benefiting effective carrier mobility by reducing the transverse field. Additionally, use of undoped channels improves low-field μ eff due to the reduction in the substrate impurity scattering. Mobility degradation due to Coulomb scattering in short-channel devices should further be reduced in the absence of pocket implants. However, high-k dielectrics are known to degrade mobility as a result of a combination of Coulomb and phonon scattering mechanisms. In order to account for inversion layer mobility degradation mechanisms for FinFET devices, a robust μ eff extraction algorithm is necessary. The mobility extraction requires accurate measurement of both gate to channel capacitance and channel current, together with reliable estimations for the parasitic Source-Drain series resistance (RSD) and the effective channel length. Unfortunately, the capacitance of short-channel length devices in the presence of large gate leakage is no longer characterized trivially. In multi-gate architectures like the FinFET, the carrier transport occurs in different crystallographic planes. For standard substrates, the current flow occurs in the (100)/(110) for the top surface and (110)/(110) for the sidewalls. The transport in these crystal planes and directions are characterized by different mobility primarily due to the anisotropy of the effective masses.

(4)

Finfet has lowerprinted gate length Lg, lower Ioff and higher Ionn compared to single gate mosfet. In low supply voltages the ION/IOFF ratio is higher for FinFET while in high supply voltages (higher than 0.72V) it is higher for bulk MOSFET. It is due to the fact that bulk Mosfet has a lower IOFF compared with FinFET while FinFET has a higher ION. In low supply voltages the OFF current of MOSFET is lower but it is closed to FinFET while the ON current of FinFET is much higher than bulk CMOS or MOSFET. As a result, the ION/IOFF ratio is higher for FinFET. However, in high supply voltages (higher than 0.72V) the ON current of bulk mosfet is getting close to the ON current of FinFET and the ION/IOFF ratio of devices are closed to each other.