Question

(T/F) The conditional signal assignment in VHDL is more compact and easy to use than the selected signal assignment.

 True False 

(T/E) The difference between Signal and constant type definitions in VHDL is that both are the same but in the constant declaration the declared variable can change by a direct assignment in the architecture module. 

True False

Answer 1

The conditional signal assignment in VHDL is more compact and easy to use than the selected signal assignment.

Ans. True

A conditional assignment always enforces a priority on the conditions.

In the conditional assignment, that priority is implied by the ordering of the expressions. In the selected assignment, you must specify all possible conditions, so there can be no priority implied.

The difference between signal and constant type definition in VHDL is that both are the same in the constant declaration, the declared variable can change by direct assignment in the architecture module.

Ans. False

Constant : A constant can have a single value of a given type and cannot be changed during the simulation. A constant is declared as follows

constant list_of_name_of_constant: type [ := initial value] ;

Variable: A variable can have a single value, as with a constant, but a variable can be updated using a variable assignment statement. The variable is updated without any delay as soon as the statement is executed. Variables must be declared inside a process (and are local to the process). The variable declaration is as follows

variable list_of_variable_names: type [ := initial value] ;

Signal: Signals are declared outside the process using the following statement:

signal list_of_signal_names: type [ := initial value] ;

A variable changes instantaneously when the variable assignment is executed. On the other hand, a signal changes a delay after the assignment expression is evaluated. If no delay is specified, the signal will change after a delta delay.