Question

Having trouble with the verilog code. Also think my ASM chart may be wrong so some help with that would be great as well thanks. Not sure if the question is linked but its a textbook question. Digital design 6th edition chapter 8 question 10.Link:  https://www.chegg.com/homework-help/Digital-Design-6th-edition-chapter-8-problem-10P-solution-9780134529561

Answer 1

//

//verilog model for given moore state machine
module moore_fsm # (
//parameter declarations for states
parameter S0 = 2'b00 ,
S1 = 2'b01 ,
S2 = 2'b10 ,
S3 = 2'b11
)(
//input port declarations
input CLK, // clock input
input Resetn, //Asynchronous active low reset input
input x,y,//binary data input
  
//output port declarations
output [1:0] out // state machine output
);
  
//internal register declarations for states
reg [1:0] current_state, next_state; // current state and next state
  
// sequential logic for present satte of the Moore FSM
always @(posedge CLK)
begin
if(Resetn==0)
current_state <= S0;// when reset=0, reset the state of the FSM to "S0" State
else
current_state <= next_state; // otherwise, next state
end
  
// combinational logic of the Moore FSM
// to determine next state
always @(current_state,x,y)
begin
case(current_state)
S0:begin
if(x==1)
next_state <= S1;
else
next_state <= S0;
end
S1:begin
if(y==1)
next_state <= S3;
else
next_state <= S2;
end
S2:begin
case ({x,y})
2'b00 : next_state <= S0;
2'b01 : next_state <= S0;
2'b10 : next_state <= S2;
2'b11 : next_state <= S3;
endcase
end
S3:begin
case ({x,y})
2'b00 : next_state <= S2;
2'b01 : next_state <= S3;
2'b10 : next_state <= S0;
2'b11 : next_state <= S0;
endcase   
end

endcase
end

// combinational logic to determine the output
// of the Moore FSM, output only depends on current state

assign out = current_state ;

endmodule
  
//testbench

// veriog testbench code for guven moore state machine
module test_fsm ;
  
//inputs
reg CLK;
reg Resetn;
reg x,y;
  
//outputs
wire [1:0] out;
  
//instantiate DUT od moore FSM
moore_fsm DUT ( .CLK(CLK),.Resetn(Resetn),.x(x),.y(y),.out(out));
  
//clock geneartion
initial begin
CLK = 0;
forever #5 CLK = ~CLK;
end
  
//reset generation
initial begin
Resetn = 0;
#10 Resetn =1 ;
end
  
//binary data input generation
initial begin
$dumpfile("dump.vcd");
$dumpvars;
x = 0;y=0; #10;
x = 0;y=1; #10;
x = 1;y=0; #10;   
x = 0;y=1; #10;
x = 1;y=1; #10;
x = 0;y=1; #10;
x = 1;y=0; #10;
x = 1;y=0; #10;
x = 1;y=0; #10;
x = 1;y=1; #10;
x = 0;y=1; #10;
x = 1;y=0; #10;
x = 0;y=1; #10;
x = 1;y=0; #10;
x = 0;y=1; #10;
x = 0;y=0; #10;
x = 1;y=0; #10;
x = 1;y=1; #10;
x = 0;y=1; #10;
$finish;
end
  
  
endmodule

// I added resetn input port just as a safety when module implemented in hardware

//simulated wavform