Question

Draw the cache tables and the state of all bits within them.

Suppose you have a 16 byte cache with 2 byte long cachelines that is 2-way set associative and write-back. Further assume that prior to processing any read/write requests the state of memory is M[a] = a, or another words, the byte at address 0 is 0, address 1 is 1, address 2 is 2, and so on. Assume an *8 bit* long address. Along with depicting the cache tables, please answer the following questions:

How many bits are devoted to the line size?

How many bits are devoted to the index?

How many bits are devoted to the tag?

Here is the sequnce of read/write requests:

    Read 0x01
    Read 0x02
    Read 0x03
    Write 0x05, Value=100
    Write 0x06, Value=101
    Write 0x07, Value=102
    Write 0x06, Value=103
    Read 0x03
    Read 0x07
    Read 0x01
    Read 0x02
    Read 0x03

How many accesses hit in the cache?

How many accesses missed?

How many times did the cache write values back to main memory?

Answer 1

GIVEN THAT

from the given data

cache size =16 bytes

cache line =2 bytes

we know that

total cache blacks=

=8 blacks

the cache given is 2 way set associative

hence

total no .of sets=

=4 sets

the total no.of bits required to address cache black

16*8

=

=7 bits

the total no.of bits required for line size

line size

2 bytes=16 bytes

=

=4 bytes (for line size)

Tag

set index

cache black

here

total number of sets=4

2 bits required for indexing

how

address size of given cache black=7 bits

i.e= (size)

tag+index+cache black=7 bits

tag+2+4=7

tag=1 bit

Tag 1 bit

Set index 2 bit

cache black 4 bits

from the given data eachb cache line helds 2 bytes

Total cache byte is 16 bytes by the following cache can be depicted

   byte 1

byte 3

byte 5

byte 7

   byte 9

   byte 11

   byte 13

byte 15

Input:

1. read 0*01

2. read 0*02

3 read 0*03

4 write 0*05 ,value=100

5 write 0*06, value=101

6 write 0*07 , value=102

7 write 0*06 , value=103

8 read 0*03

9 read 0*07

10 read 0*01

11 read 0*02

12 read 0*03,

we need an update to main memory can be done at the end

important points to remember:

In case of miss cache , if needs as entire from main memory

Example

if it wants to read 0*00

when in case of miss

if reads 0*00 and 0*2 enitre black

There are total in struction-12

Instruction no miss/hit

1 miss

2 miss

3 hit

4 miss and upload in cache

5 miss and updates in cache

6 hit and updates in cache

7 hit and updates in cache[updates at the end it is write black]

8 hit

9 hit

10 hit

11 hit

12 hit

total no.of bits=8

total no.of misses=4

no,of updates=3