Question

Instruction to assigned to each processor. ARM Cortex-A12

1. Draw neatly architectural or block diagram of the selected processor. Identify the following listed below features and explain briefly.
2. Pipelining and stages
3. Memory or Cache
4. Fetch Unit and Decode units
5. Instruction issue policy
6. Register Renaming
7. Reorder Buffer
8. Reservation Station
9. Branch Prediction
10. Execution Units
11. Processor speed
12. Number of Cores
13. Number of Threads 36
14. Levels of cache and separate or shared cache or instruction and data cache
15. Hyper-Threading or TLP

Answer 1

ARM Cortex-A12 Processor:

Architecture:

Pipelining and stages:

Cortex-A12 is the first mid-range solution specifically designed for this cost sensitive market. It features a new, ground up pipeline design, offering 11-stage full out-of-order 32b processing capabilities, and will deliver today’s high end feature sets in tomorrow’s mid-range devices – for lower cost and lower power consumption. While the Cortex-A12 builds on the sweet spot identified by the Cortex-A9, Cortex-A9 was designed in it’s day (2008) to be a very high-end mobile processor – and delivered on that goal from 2010-2012 and it’s versatility allowed it to part of chip shipments of over a billion units!

Memory or Cache:

ARM Cortex – A12 was designed by L1 cache – 32-64 Kib I, 32 KiB D

And L2 cache – 256 KiB – 8 MiB

Fetch Unit and Decode units:

The fetch unit contains the instruction cache controller and it’s associated linefill buffer. The ARM Cortex – A12 instruction cache is a two way set associative and uses Virtually indexed physical tagged cache lines holding upto 16 A 32 instructions.

Instruction issue policy: Issues come into picture when the instructions are decoded into micro-ops, renamed instructions are dispatched into the issue queues and then micro-ops are issued from the issue queues when their operands are available. Everything up to the issue queue is handled in order, while issuing can be handled out of order in the Cortex A12 (in most cases, more on this later).

Register Renaming:

register renaming is a technique that abstracts logical registers from physical registers. Every logical register has a set of physical registers associated with it. While a programmer in assembly language refers for instance to a logical register accu, the processor transposes this name to one specific physical register on the fly.

Reservation Station: Reservation stations permit the CPU to fetch and re-use a data value as soon as it has been computed, rather than waiting for it to be stored in a register and re-read. When instructions are issued, they can designate the reservation station from which they want their input to read. When multiple instructions need to write to the same register, all can proceed and only the (logically) last one need actually be written. It checks if the operands are available (RAW) and if execution unit is free (Structural hazard) before starting execution.

Branch Prediction

Branch prediction is a technique used in CPU design that attempts to guess the outcome of a conditional operation and prepare for the most likely result. A digital circuit that performs this operation is known as a branch predictor

Processor speed: Speculative speed execution pipeline is 3.00 DMIPS/MHz/core

Number of Cores: The ARM Cortex-A12 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It provides up to 4 cache-coherent cores.

Hyper threading : is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 microprocessors. hyper-threading was criticised for energy inefficiency. For example, specialist low-power CPU design company ARM stated that simultaneous multithreading can use up to 46% more power than ordinary dual-core designs.

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